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DTSTART:20001029T040000
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UID:pretalx-38c3-UDBPYF@cfp.cccv.de
DTSTART;TZID=CET:20241229T144500
DTEND;TZID=CET:20241229T152500
DESCRIPTION:With the availability of robust silicon-proven open-source tool
 s\, IPs\, and process design kits (PDKs)\, it is now possible to build com
 plex chips without industry tools. This is exactly what we did to design o
 ur first open-everything FABulous FPGA\, which is an example of open silic
 on that is designed and programmed entirely with open tools.\n\nProduced i
 n the Skywater 130nm process node\, our chip features 672 LUTs (each with 
 4 inputs and a flop)\, 6 DSP blocks (8x8 bit multipliers with 20-bit accum
 ulators)\, 8 BRAMs (with 1KB each)\, and 12 register file primitives (each
  having 32 4-bit words with 1 write and 2 read ports). The resources are s
 ufficient to run\, for instance\, a small RISC-V system on the fabric. The
  FPGA comes with a small board that is designed to fit into an audio casse
 tte case and that can be programmed directly via an USB interface. Moreove
 r\, the FPGA supports partial reconfiguration\, which allows us to swap th
 e logic of parts of the FPGA while continuing operation in the rest of the
  chip.\n\nThe chip was designed with the help of the versatile FABulous fr
 amework\, which integrates several further open-source projects\, includin
 g Yosys\, nextpnr\, the Verilator\, OpenRAM\, and the OpenLane tool suite.
  FABulous was used for various embedded FPGAs\, including multiple designs
  manufactured in the TSMC 28nm process node.\n\nThe talk will discuss and 
 analyze differences and similarities with industry FPGAs and dive into des
 ign decision taken and optimizations applied to deliver good quality of re
 sults (with respect to area cost and performance). The talk will highlight
  state-of-the-art in open-source FPGA chip design and provide a deeper tha
 n usual discussion on the design principles of these devices.
DTSTAMP:20241227T122546Z
LOCATION:Saal GLITCH
SUMMARY:The Design Decisions behind the first Open-Everything FABulous FPGA
  - Dirk
URL:https://fahrplan.events.ccc.de/congress/2024/fahrplan/talk/UDBPYF/
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