Schedule 37th Chaos Communication Congress

SpinalHDL / VexRiscv / NaxRiscv main dev

Developing open-source FPGA designs since 2015, i'm the main dev of :
- SpinalHDL : An alternative to VHDL / Verilog
- VexRiscv : An in-order linux SMP capable softcore
- NaxRiscv : An out-of-order debian SMP capable softcore

I'm trying mostly to push forward the hardware design flow by mixing some software concepts into the hardware elaboration flow.

Contact

E-Mail: charles.papon.90@gmail.com